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2008
IEEE
78views Hardware» more  DATE 2008»
16 years 1 months ago
Simultaneous FU and Register Binding Based on Network Flow Method
– With the rapid increase of design complexity and the decrease of device features in nano-scale technologies, interconnection optimization in digital systems becomes more and mo...
Jason Cong, Junjuan Xu
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
16 years 1 months ago
A Single-supply True Voltage Level Shifter
When a signal traverses on-chip voltage domains, a level shifter is required. Inverters can handle a high to low voltage shift with minimal leakage. For a low to high voltage leve...
Rajesh Garg, Gagandeep Mallarapu, Sunil P. Khatri
DATE
2008
IEEE
112views Hardware» more  DATE 2008»
16 years 1 months ago
Tool Support for Incremental Failure Mode and Effects Analysis of Component-Based Systems
Failure Mode and Effects Analysis (FMEA) is a wellknown technique widely used for safety assessment in the area of safety-critical systems. However, FMEA is traditionally done man...
Jonas Elmqvist, Simin Nadjm-Tehrani
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
16 years 1 months ago
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
Sanghyun Park, Aviral Shrivastava, Yunheung Paek
DATE
2008
IEEE
113views Hardware» more  DATE 2008»
16 years 1 months ago
Random Stimulus Generation using Entropy and XOR Constraints
Despite the growing research effort in formal verification, constraint-based random simulation remains an integral part of design validation, especially for large design componen...
Stephen Plaza, Igor L. Markov, Valeria Bertacco