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ACMSE
2006
ACM
16 years 24 days ago
A SAT-based solver for Q-ALL SAT
Although the satisfiability problem (SAT) is NP-complete, state-of-the-art solvers for SAT can solve instances that are considered to be very hard. Emerging applications demand t...
Ben Browning, Anja Remshagen
ASPDAC
2006
ACM
176views Hardware» more  ASPDAC 2006»
16 years 24 days ago
Conversion of reference C code to dataflow model: H.264 encoder case study
– Model-based design is widely accepted in developing complex embedded system under intense time-to-market pressure. While it promises improved design productivity, the main bott...
Hyeyoung Hwang, Taewook Oh, Hyunuk Jung, Soonhoi H...
ASPDAC
2006
ACM
109views Hardware» more  ASPDAC 2006»
16 years 24 days ago
Cycle error correction in asynchronous clock modeling for cycle-based simulation
— As the complexity of SoCs is increasing, hardware/software co-verification becomes an important part of system verification. C-level cycle-based simulation could be an efficien...
Junghee Lee, Joonhwan Yi
189
Voted
ASPDAC
2006
ACM
288views Hardware» more  ASPDAC 2006»
16 years 24 days ago
Algorithms and DSP implementation of H.264/AVC
Abstract - This survey paper intends to provide a comprehensive coverage of the techniques that are pertinent to the processor-based implementation of H.264/AVC video codec, partic...
Hung-Chih Lin, Yu-Jen Wang, Kai-Ting Cheng, Shang-...
ASPDAC
2006
ACM
130views Hardware» more  ASPDAC 2006»
16 years 24 days ago
Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops
Statistical timing analysis has been widely applied to predict the timing yield of VLSI circuits when process variations become significant. Existing statistical latch timing met...
Lizheng Zhang, Jeng-Liang Tsai, Weijen Chen, Yuhen...