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DCC
2006
IEEE
16 years 6 months ago
Evaluation codes and plane valuations
Abstract. We apply tools coming from singularity theory, as Hamburger-Noether expansions, and from valuation theory, as generating sequences, to explicitly describe order functions...
C. Galindo, M. Sanchis
DCC
2006
IEEE
16 years 6 months ago
Optimal Prefix Codes for Some Families of Two-Dimensional Geometric Distributions
Lossless compression is studied for pairs of independent integer-valued symbols emitted by a source with a geometric probability distribution of parameter q (0, 1). Optimal prefix...
Alfredo Viola, Frédérique Bassino, G...
ICCAD
2006
IEEE
113views Hardware» more  ICCAD 2006»
16 years 3 months ago
A novel framework for faster-than-at-speed delay test considering IR-drop effects
Faster-than-at-speed test have been proposed to detect small delay defects. While these techniques increase the test frequency to reduce the positive slack of the path, they exace...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
ICCAD
2006
IEEE
95views Hardware» more  ICCAD 2006»
16 years 3 months ago
Timing model reduction for hierarchical timing analysis
— In this paper, we propose a timing model reduction algorithm for hierarchical timing analysis based on a bicliquestar replacement technique. In hierarchical timing analysis, ea...
Shuo Zhou, Yi Zhu, Yuanfang Hu, Ronald L. Graham, ...
ICCAD
2006
IEEE
113views Hardware» more  ICCAD 2006»
16 years 3 months ago
Layer minimization of escape routing in area array packaging
We devise a central triangular sequence to minimize the escape routing layers in area array packaging. We use a network flow model to analyze the bottleneck of the routable pins. ...
Renshen Wang, Rui Shi, Chung-Kuan Cheng