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DAC
2005
ACM
16 years 7 months ago
Efficient SAT solving: beyond supercubes
SAT (Boolean satisfiability) has become the primary Boolean reasoning engine for many EDA applications, so the efficiency of SAT solving is of great practical importance. Recently...
Domagoj Babic, Jesse D. Bingham, Alan J. Hu
DAC
2005
ACM
16 years 7 months ago
Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration
Many reconfigurable architectures offer partial dynamic configurability, but current system-level tools cannot guarantee feasible implementations when exploiting this feature. We ...
Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. D...
DAC
2005
ACM
16 years 7 months ago
Segregation by primary phase factors: a full-wave algorithm for model order reduction
Existing Full-wave Model Order Reduction (FMOR) approaches are based on Expanded Taylor Series Approximations (ETAS) of the oscillatory full-wave system matrix. The accuracy of su...
Thomas J. Klemas, Luca Daniel, Jacob K. White
DAC
2005
ACM
16 years 7 months ago
FPGA technology mapping: a study of optimality
This paper attempts to quantify the optimality of FPGA technology mapping algorithms. We develop an algorithm, based on Boolean satisfiability (SAT), that is able to map a small s...
Andrew C. Ling, Deshanand P. Singh, Stephen Dean B...
DAC
2005
ACM
16 years 7 months ago
Approximate VCCs: a new characterization of multimedia workloads for system-level MpSoC design
System-level design methods specifically targeted towards multimedia applications have recently received a lot of attention. Multimedia workloads are known to have a high degree o...
Yanhong Liu, Samarjit Chakraborty, Wei Tsang Ooi