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DDECS
2009
IEEE
106views Hardware» more  DDECS 2009»
16 years 1 months ago
Forward and backward guarding in early output logic
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...
Charlie Brej, Doug Edwards
DSD
2009
IEEE
111views Hardware» more  DSD 2009»
16 years 1 months ago
Robustness Check for Multiple Faults Using Formal Techniques
Feature sizes in VLSI circuits are steadily shrinking. This results in increasing susceptibility to soft errors, e.g. due to environmental radiation. Precautions against soft error...
Stefan Frehse, Görschwin Fey, André S&...
DSN
2009
IEEE
16 years 1 months ago
I-JVM: a Java Virtual Machine for component isolation in OSGi
The OSGi framework is a Java-based, centralized, component oriented platform. It is being widely adopted as an execution environment for the development of extensible applications...
Nicolas Geoffray, Gaël Thomas, Gilles Muller,...
DSN
2009
IEEE
16 years 1 months ago
Report generation for simulation traces with Traviando
Any model-based evaluation of the dependability of a system requires validation and verification to justify that its results are meaningful. Modern modeling frameworks enable us ...
Peter Kemper
EMS
2009
IEEE
16 years 1 months ago
Modelling Periodic Data Dissemination in Wireless Sensor Networks
—Epidemic-based communications, or “gossiping”, provides a robust and scalable method for maintaining a knowledge base in a sensor network faced with an unpredictable network...
Graham Williamson, Davide Cellai, Simon A. Dobson,...