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MICRO
2009
IEEE
124views Hardware» more  MICRO 2009»
16 years 1 months ago
ZerehCache: armoring cache architectures in high defect density technologies
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
MICRO
2009
IEEE
147views Hardware» more  MICRO 2009»
16 years 1 months ago
Complexity effective memory access scheduling for many-core accelerator architectures
Modern DRAM systems rely on memory controllers that employ out-of-order scheduling to maximize row access locality and bank-level parallelism, which in turn maximizes DRAM bandwid...
George L. Yuan, Ali Bakhoda, Tor M. Aamodt
MICRO
2009
IEEE
132views Hardware» more  MICRO 2009»
16 years 1 months ago
Finding concurrency bugs with context-aware communication graphs
Incorrect thread synchronization often leads to concurrency bugs that manifest nondeterministically and are difficult to detect and fix. Past work on detecting concurrency bugs ...
Brandon Lucia, Luis Ceze
MICRO
2009
IEEE
134views Hardware» more  MICRO 2009»
16 years 1 months ago
A case for dynamic frequency tuning in on-chip networks
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...
Asit K. Mishra, Reetuparna Das, Soumya Eachempati,...
AAECC
2009
Springer
136views Algorithms» more  AAECC 2009»
16 years 1 months ago
There Are Not Non-obvious Cyclic Affine-invariant Codes
We show that an affine-invariant code C of length pm is not permutation equivalent to a cyclic code except in the obvious cases: m = 1 or C is either {0}, the repetition code or it...
José Joaquín Bernal, Ángel de...
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