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FDL
2005
IEEE
16 years 14 days ago
Automatic synthesis of the Hardware/Software Interface
Although Moore’s Law enables a huge number of components to be integrated into a single chip, design methods that will allow system architects to put the components together to ...
Francesco Regazzoni, André C. Nácul,...
FPT
2005
IEEE
181views Hardware» more  FPT 2005»
16 years 14 days ago
Hardware-Accelerated SSH on Self-Reconfigurable Systems
The performance of security applications can be greatly improved by accelerating the cryptographic algorithms in hardware. In this paper, an implementation of the Secure Shell (SS...
Ivan Gonzalez, Francisco J. Gomez-Arribas, Sergio ...
FPT
2005
IEEE
198views Hardware» more  FPT 2005»
16 years 14 days ago
From TLM to FPGA: Rapid Prototyping with SystemC and Transaction Level Modeling
We describe a communication-centric design methodology with SystemC that allows for efficient FPGA prototype generation of transaction level models (TLM). Using a framework compr...
Wolfgang Klingauf, Robert Günzel
FPT
2005
IEEE
134views Hardware» more  FPT 2005»
16 years 14 days ago
Post-Silicon Debug Using Programmable Logic Cores
Producing a functionally correct integrated circuit is becoming increasingly difficult. No matter how careful a designer is, there will always be integrated circuits that are fabr...
Bradley R. Quinton, Steven J. E. Wilton
GLVLSI
2005
IEEE
118views VLSI» more  GLVLSI 2005»
16 years 14 days ago
A continuous time markov decision process based on-chip buffer allocation methodology
We have presented an optimal on-chip buffer allocation and buffer insertion methodology which uses stochastic models of the architecture. This methodology uses finite buffer s...
Sankalp Kallakuri, Nattawut Thepayasuwan, Alex Dob...