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ISCAS
2005
IEEE
139views Hardware» more  ISCAS 2005»
16 years 4 days ago
A frequency-domain SIR maximizing time-domain equalizer for VDSL systems
In this paper we propose a semi-blind time domain equalizer (TEQ) design method that maximize SIR (signal-tointerference ratio) in frequency domain for VDSL systems. The proposed ...
Yuan-Pei Lin, Li-Han Liang, Pei-Ju Chung, See-May ...
143
Voted
ISMVL
2005
IEEE
86views Hardware» more  ISMVL 2005»
16 years 4 days ago
Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders
A novel duplex asynchronous data-transfer scheme based on multiple-valued encoding is proposed for interleaving in Low-Density Parity-Check (LDPC) decoders, where high-throughput ...
Naoya Onizawa, Akira Mochizuki, Takahiro Hanyu
ISORC
2005
IEEE
16 years 4 days ago
Object-Reuse for More Predictable Real-Time Java Behavior
One of the problems with Java for real-time systems is the unpredictable behavior of garbage collection (GC). GC introduces unexpected load and causes undesirable delays for real-...
Jameela Al-Jaroodi, Nader Mohamed
ISPDC
2005
IEEE
16 years 4 days ago
Enforcing consistency during the adaptation of a parallel component
Abstract. Grid architectures are execution environments that are known to be at the same time distributed, parallel, heterogeneous and dynamic. While current tools focus solutions ...
Jérémy Buisson, Françoise And...
193
Voted
ITCC
2005
IEEE
16 years 4 days ago
AES Power Attack Based on Induced Cache Miss and Countermeasure
This paper presents a new attack against a software implementation of the Advanced Encryption Standard. The attack aims at flushing elements of the SBOX from the cache, thus indu...
Guido Bertoni, Vittorio Zaccaria, Luca Breveglieri...