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ISCAS
2005
IEEE
122views Hardware» more  ISCAS 2005»
16 years 4 days ago
Linear and nonlinear macromodels for power/signal integrity
— In this paper, a systematic methodology for the assessment of Power/Signal Integrity effects in high-speed communication and information systems is presented. The proposed meth...
Stefano Grivet-Talocia, Igor S. Stievano, Ivan A. ...
ISCAS
2005
IEEE
229views Hardware» more  ISCAS 2005»
16 years 4 days ago
Comparison of two class E amplifiers for EER transmitter
- This paper compares two types of class E power amplifier and studies their applicability in EER (Envelope Elimination and Restoration) transmitter. In EER applications one of the...
Antti Heiskanen, Timo Rahkonen
ISCAS
2005
IEEE
113views Hardware» more  ISCAS 2005»
16 years 4 days ago
On the robustness of an analog VLSI implementation of a time encoding machine
Abstract— Time encoding is a mechanism for representing the information contained in a continuous time, bandlimited, analog signal as the zero-crossings of a binary signal. Time ...
Peter R. Kinget, Aurel A. Lazar, Laszlo T. Toth
ISCAS
2005
IEEE
130views Hardware» more  ISCAS 2005»
16 years 4 days ago
Smart bio-laboratories of the future
Abstract— Recent advances in genomic research and biotechnology have led to an increased level of technological sophistication in today’s biology laboratories. With the promisi...
See-Kiong Ng
ISCAS
2005
IEEE
158views Hardware» more  ISCAS 2005»
16 years 4 days ago
Designing optimized pipelined global interconnects: algorithms and methodology impact
— As across-chip wire delays exceed a clock cycle, interconnect pipelining becomes essential. However, the arbitrary insertion of flip-flops can change the differentials of lat...
Vidyasagar Nookala, Sachin S. Sapatnekar