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DAC
2007
ACM
16 years 7 months ago
Modeling the Function Cache for Worst-Case Execution Time Analysis
Static worst-case execution time (WCET) analysis is done by modeling the hardware behavior. In this paper we describe a WCET analysis technique to analyze systems with function ca...
Raimund Kirner, Martin Schoeberl
DAC
2007
ACM
16 years 7 months ago
Placement of 3D ICs with Thermal and Interlayer Via Considerations
Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during g...
Brent Goplen, Sachin S. Sapatnekar
DAC
2007
ACM
16 years 7 months ago
Enhancing FPGA Performance for Arithmetic Circuits
FPGAs offer flexibility and cost-effectiveness that ASICs cannot match; however, their performance is quite poor in comparison, especially for arithmetic dominated circuits. To ad...
Philip Brisk, Ajay K. Verma, Paolo Ienne, Hadi Par...
DAC
2007
ACM
16 years 7 months ago
Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations
Due to increased variability trends in nanoscale integrated circuits, statistical circuit analysis has become essential. We present a novel method for post-silicon analysis that g...
Qunzeng Liu, Sachin S. Sapatnekar
MICCAI
2007
Springer
16 years 7 months ago
Generating Fiber Crossing Phantoms Out of Experimental DWIs
In Diffusion Tensor Imaging (DTI), differently oriented fiber bundles inside one voxel are incorrectly modeled by a single tensor. High Angular Resolution Diffusion Imaging (HARDI)...
Matthan Caan, Anne Willem de Vries, Ganesh Khedoe,...