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209
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HOTI
2008
IEEE
16 years 1 months ago
Network Processing on an SPE Core in Cell Broadband Engine
Cell Broadband EngineTM is a multi-core system on a chip and is composed of a general-purpose Power Processing Element (PPE) and eight Synergistic Processing Elements (SPEs). Its ...
Yuji Kawamura, Takeshi Yamazaki, Hiroshi Kyusojin,...
163
Voted
HOTI
2008
IEEE
16 years 1 months ago
Design Exploration of Optical Interconnection Networks for Chip Multiprocessors
The Network-on-Chip (NoC) paradigm has emerged as a promising solution for providing connectivity among the increasing number of cores that get integrated into both systems-onchip...
Michele Petracca, Benjamin G. Lee, Keren Bergman, ...
163
Voted
HOTI
2008
IEEE
16 years 1 months ago
Low Power Passive Equalizer Design for Computer Memory Links
Several types of low power passive equalizer is proposed and optimized in this work. The equalizer topologies include T-junction, parallel R-C and series R-L structures. These str...
Ling Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang,...
189
Voted
HPDC
2008
IEEE
16 years 1 months ago
XenLoop: a transparent high performance inter-vm network loopback
Advances in virtualization technology have focused mainly on strengthening the isolation barrier between virtual machines (VMs) that are co-resident within a single physical machi...
Jian Wang, Kwame-Lante Wright, Kartik Gopalan
218
Voted
HPDC
2008
IEEE
16 years 1 months ago
StoreGPU: exploiting graphics processing units to accelerate distributed storage systems
Today Graphics Processing Units (GPUs) are a largely underexploited resource on existing desktops and a possible costeffective enhancement to high-performance systems. To date, mo...
Samer Al-Kiswany, Abdullah Gharaibeh, Elizeu Santo...
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