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ISCA
2008
IEEE
113views Hardware» more  ISCA 2008»
16 years 1 months ago
A Two-Level Load/Store Queue Based on Execution Locality
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
Miquel Pericàs, Adrián Cristal, Fran...
180
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ISCA
2008
IEEE
139views Hardware» more  ISCA 2008»
16 years 1 months ago
Atom-Aid: Detecting and Surviving Atomicity Violations
Writing shared-memory parallel programs is error-prone. Among the concurrency errors that programmers often face are atomicity violations, which are especially challenging. They h...
Brandon Lucia, Joseph Devietti, Karin Strauss, Lui...
ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
16 years 1 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
ISCA
2008
IEEE
148views Hardware» more  ISCA 2008»
16 years 1 months ago
Atomic Vector Operations on Chip Multiprocessors
The current trend is for processors to deliver dramatic improvements in parallel performance while only modestly improving serial performance. Parallel performance is harvested th...
Sanjeev Kumar, Daehyun Kim, Mikhail Smelyanskiy, Y...
ISCAS
2008
IEEE
217views Hardware» more  ISCAS 2008»
16 years 1 months ago
Approximate L0 constrained non-negative matrix and tensor factorization
— Non-negative matrix factorization (NMF), i.e. V ≈ WH where both V, W and H are non-negative has become a widely used blind source separation technique due to its part based r...
Morten Mørup, Kristoffer Hougaard Madsen, L...
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