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ISCAS
2007
IEEE
132views Hardware» more  ISCAS 2007»
16 years 1 months ago
On-Line Histogram Equalization for Flash ADC
— We present theory, design and measurement results for an on-line histogram equalization algorithm implemented on a 750MS/s 6b flash analog to digital converter in standard 0.3...
Yanyi Liu Wong, Marc H. Cohen, Pamela Abshire
ISVLSI
2007
IEEE
204views VLSI» more  ISVLSI 2007»
16 years 1 months ago
Designing Memory Subsystems Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance ...
Mahmoud Ben Naser, Yao Guo, Csaba Andras Moritz
NOCS
2007
IEEE
16 years 1 months ago
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing
Dynamic routing can substantially enhance the quality of service for multiprocessor communication, and can provide intelligent adaptation of faulty links during run time. Implemen...
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. C...
PG
2007
IEEE
16 years 1 months ago
Multilinear Motion Synthesis with Level-of-Detail Controls
Interactive animation systems often use a level-of-detail (LOD) control to reduce the computational cost by eliminating unperceivable details of the scene. Most methods employ a m...
Tomohiko Mukai, Shigeru Kuriyama
VTC
2007
IEEE
16 years 1 months ago
Packet Centric vs. Radio Centric Link Layer Approaches: A Quantitative Analysis
Abstract— A well-known concept to adapt the transmitted payload to the current channel capacity is to perform segmentation of the uncoded user payload. In [1], a new cross layera...
Francesco Rossetto, Michael Meyer, Michele Zorzi