Sciweavers

6202 search results - page 953 / 1241
» Without Loss of Generality
Sort
View
DAC
2009
ACM
16 years 1 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
IDTRUST
2009
ACM
16 years 1 months ago
Usable trust anchor management
Security in browsers is based upon users trusting a set of root Certificate Authorities (called Trust Anchors) which they may know little or nothing about. Browser vendors face a...
Massimiliano Pala, Scott A. Rea
ISPD
2009
ACM
141views Hardware» more  ISPD 2009»
16 years 1 months ago
A faster approximation scheme for timing driven minimum cost layer assignment
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
Shiyan Hu, Zhuo Li, Charles J. Alpert
MOBIHOC
2009
ACM
16 years 1 months ago
Revenue generation for truthful spectrum auction in dynamic spectrum access
Spectrum is a critical yet scarce resource and it has been shown that dynamic spectrum access can significantly improve spectrum utilization. To achieve this, it is important to ...
Juncheng Jia, Qian Zhang, Qin Zhang, Mingyan Liu
PLDI
2009
ACM
16 years 1 months ago
A language for information flow: dynamic tracking in multiple interdependent dimensions
This paper presents λI , a language for dynamic tracking of information flow across multiple, interdependent dimensions of information. Typical dimensions of interest are integr...
Avraham Shinnar, Marco Pistoia, Anindya Banerjee