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» Wireplanning in logic synthesis
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ISQED
2002
IEEE
103views Hardware» more  ISQED 2002»
15 years 11 months ago
Synthesis of Selectively Clocked Skewed Logic Circuits
Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaush...
APSEC
2000
IEEE
15 years 10 months ago
A process logic for distributed system synthesis
Yoshinao Isobe, Kazuhito Ohmaki
DAC
1994
ACM
15 years 10 months ago
Layout Driven Logic Synthesis for FPGAs
Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, ...
DATE
2004
IEEE
114views Hardware» more  DATE 2004»
15 years 9 months ago
Synthesis of Reversible Logic
Abhinav Agrawal, Niraj K. Jha