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ISVLSI
2007
IEEE
184views VLSI» more  ISVLSI 2007»
16 years 20 days ago
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
INFOCOM
2002
IEEE
15 years 11 months ago
Stability of a Multicast Tree
— Most of the currently deployed multicast protocols (e.g. DVMRP, PIM, MOSPF) build one shortest path multicast tree per sender, the tree being rooted at the sender’s subnetwor...
Piet Van Mieghem, Milena Janic
ICETET
2009
IEEE
16 years 1 months ago
Low Energy Tree Based Network on Chip Architectures Using Homogeneous Routers for Bandwidth and Latency Constrained Multimedia A
Abstract— Design of Network on chip architectures for multimedia applications is being widely studied. This involves design decisions at various levels of hierarchy. Topology des...
Deepak Majeti, Aditya Pasalapudi, Kishore Yalamanc...
JVA
2006
IEEE
16 years 12 days ago
Natural Deduction Calculus for Computation Tree Logic
We present a natural deduction calculus for the computation tree logic CTL defined with the full set of classical and temporal logic operators. The system extends the natural ded...
Alexander Bolotov, Oleg Grigoriev, Vasilyi Shangin
CADE
2001
Springer
15 years 11 months ago
Approximating Dependency Graphs Using Tree Automata Techniques
The dependency pair method of Arts and Giesl is the most powerful technique for proving termination of term rewrite systems automatically. We show that the method can be improved b...
Aart Middeldorp