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ICCD
2004
IEEE
103views Hardware» more  ICCD 2004»
16 years 3 months ago
Design-Space Exploration of Power-Aware On/Off Interconnection Networks
— With power a major limiting factor in the design of scalable interconnected systems, power-aware networks will become inherent components of single-chip and multi-chip systems....
Vassos Soteriou, Li-Shiuan Peh
PVM
2007
Springer
16 years 1 months ago
Using CMT in SCTP-Based MPI to Exploit Multiple Interfaces in Cluster Nodes
Many existing clusters use inexpensive Gigabit Ethernet and often have multiple interfaces cards to improve bandwidth and enhance fault tolerance. We investigate the use of Concurr...
Brad Penoff, Mike Tsai, Janardhan R. Iyengar, Alan...
ASAP
2006
IEEE
110views Hardware» more  ASAP 2006»
16 years 29 days ago
Loop Transformation Methodologies for Array-Oriented Memory Management
Abstract – The storage requirements in data-dominant signal processing systems, whose behavior is described by arraybased, loop-organized algorithmic specifications, have an imp...
Florin Balasa, Per Gunnar Kjeldsberg, Martin Palko...
SCOPES
2005
Springer
16 years 11 days ago
The Bit-reversal SDRAM Address Mapping
The performance contributions of SDRAM address mapping techniques in the main memory of an embedded system are studied and examined. While spatial locality existing in the access ...
Jun Shao, Brian T. Davis
SC
2004
ACM
16 years 9 days ago
Using Hardware Counters to Automatically Improve Memory Performance
In this paper, we introduce a profile-driven online page migration scheme and investigate its impact on the performance of multithreaded applications. We use lightweight, inexpens...
Mustafa M. Tikir, Jeffrey K. Hollingsworth