We formally define--at the stream transformer level--a class of synchronous circuits that tolerate any variability in the latency of their environment. We study behavioral properti...
Sava Krstic, Jordi Cortadella, Michael Kishinevsky...
Intertask/interprocess synchronization overheads may be significant in a multiprocessor-shared memory System-on-a-Chip implementation. These overheads are observed in terms of loc...
Bilge Saglam Akgul, Jaehwan Lee, Vincent John Moon...
Caching is a proven means to improve scalability and availability of software systems as well as to reduce latency of user requests. In contrast to Web caching where single Web ob...
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
We describe a social visualization system that monitors the vocal arousal levels of the participants in a simulated twoparty employment negotiation. In a 3x2 factorial experiment ...
Michael Nowak, Juho Kim, Nam Wook Kim, Clifford Na...