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TC
2011
15 years 1 months ago
Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines
—Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
ISCC
2009
IEEE
163views Communications» more  ISCC 2009»
16 years 1 months ago
Distributed parallel scheduling algorithms for high-speed virtual output queuing switches
Abstract—This paper presents a novel scalable switching architecture for input queued switches with its proper arbitration algorithms. In contrast to traditional switching archit...
Lotfi Mhamdi, Mounir Hamdi
CAISE
2005
Springer
16 years 4 days ago
Dynamic Load Balancing of Virtualized Database Services Using Hints and Load Forecasting
Abstract. Future database application systems will be designed as Service Oriented Architectures (SOAs), in contrast to today’s monolithic architectures. The decomposition in man...
Daniel Gmach, Stefan Krompass, Stefan Seltzsam, Ma...
FPL
2004
Springer
164views Hardware» more  FPL 2004»
15 years 10 months ago
Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors
Abstract. In Reconfigurable Systems-On-Chip (RSoCs), operating systems can primarily (1) manage the sharing of limited reconfigurable resources, and (2) support communication betwe...
Miljan Vuletic, Laura Pozzi, Paolo Ienne
CONEXT
2009
ACM
15 years 7 months ago
Virtually eliminating router bugs
Software bugs in routers lead to network outages, security vulnerabilities, and other unexpected behavior. Rather than simply crashing the router, bugs can violate protocol semant...
Eric Keller, Minlan Yu, Matthew Caesar, Jennifer R...