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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
15 years 11 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
EUROPAR
2009
Springer
15 years 11 months ago
MyriXen: Message Passing in Xen Virtual Machines over Myrinet and Ethernet
Data access in HPC infrastructures is realized via user-level networking and OS-bypass techniques through which nodes can communicate with high bandwidth and low-latency. Virtualiz...
Anastassios Nanos, Nectarios Koziris
CASES
2007
ACM
15 years 10 months ago
A fast and generic hybrid simulation approach using C virtual machine
Instruction Set Simulators (ISSes) are important tools for cross-platform software development. The simulation speed is a major concern and many approaches have been proposed to i...
Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Asch...
CCGRID
2009
IEEE
15 years 10 months ago
Failure-Aware Construction and Reconfiguration of Distributed Virtual Machines for High Availability Computing
In large-scale clusters and computational grids, component failures become norms instead of exceptions. Failure occurrence as well as its impact on system performance and operatio...
Song Fu
ASPLOS
2010
ACM
16 years 1 months ago
Virtualized and flexible ECC for main memory
We present a general scheme for virtualizing main memory errorcorrection mechanisms, which map redundant information needed to correct errors into the memory namespace itself. We ...
Doe Hyun Yoon, Mattan Erez