1093 search results - page 35 / 219 » Verifying VLSI Circuits |
151
click to vote
GLVLSI
1998
IEEE
15 years 10 months ago
1998
IEEE
In this paper we address the problem of optimizing mixed CMOS BiCMOS circuits. The problem is formulated as a constrained combinatorial optimization problem and solved using an ta...
153
click to vote
GLVLSI
2003
IEEE
15 years 11 months ago
2003
IEEE
Modeling on-chip inductive effects for interconnects of multigigahertz microprocessors remains challenging. SPICE simulation of these effects is very slow because of the large num...
135
click to vote
ICCAD
2004
IEEE
16 years 2 months ago
2004
IEEE
Abstract— This paper presents a post-route, timingconstrained gate-sizing algorithm for crosstalk reduction. Gate-sizing has emerged as a practical and feasible method to reduce ...
163
click to vote
EH
2003
IEEE
15 years 11 months ago
2003
IEEE
This paper describes a multi-objective Evolutionary Algorithm (EA) system for the synthesis of efficient non-linear VLSI circuit modules. The EA takes the specification for a no...
327
click to vote
ARITH
2011
IEEE
14 years 6 months ago
2011
IEEE
— This paper presents a number of new high-radix ripple-carry adder designs based on Ling’s addition technique and a recently-published expansion thereof. The proposed adders a...