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» Verifying VLSI Circuits
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ISPD
2004
ACM
92views Hardware» more  ISPD 2004»
15 years 11 months ago
A predictive distributed congestion metric and its application to technology mapping
Due to increasing design complexity, routing congestion has become a critical problem in VLSI designs. This paper introduces a distributed metric to predict routing congestion for...
Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant S...
DFT
2003
IEEE
98views VLSI» more  DFT 2003»
15 years 11 months ago
Constrained ATPG for Broadside Transition Testing
In this paper, we propose a new concept of testing only functionally testable transition faults in Broadside Transition testing via a novel constrained ATPG. For each functionally...
Xiao Liu, Michael S. Hsiao
DFT
2003
IEEE
114views VLSI» more  DFT 2003»
15 years 11 months ago
CodSim -- A Combined Delay Fault Simulator
Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they only model a subset of delay defect behaviors. To solve this ...
Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, We...
IPPS
2003
IEEE
15 years 11 months ago
Parallel Tabu Search in a Heterogeneous Environment
In this paper, we discuss a parallel tabu search algorithm with implementation in a heterogeneous environment. Two parallelization strategies are integrated: functional decomposit...
Ahmad A. Al-Yamani, Sadiq M. Sait, Hassan Barada, ...
ISVLSI
2003
IEEE
157views VLSI» more  ISVLSI 2003»
15 years 11 months ago
Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random...
Shalini Ghosh, Sugato Basu, Nur A. Touba