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CAV
1999
Springer
119views Hardware» more  CAV 1999»
15 years 11 months ago
Exploiting Positive Equality in a Logic of Equality with Uninterpreted Functions
Abstract. In using the logic of equality with unininterpreted functions to verify hardware systems, specific characteristics of the formula describing the correctness condition ca...
Randal E. Bryant, Steven M. German, Miroslav N. Ve...
MICRO
1999
IEEE
105views Hardware» more  MICRO 1999»
15 years 11 months ago
DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design
Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that ...
Todd M. Austin
SAC
2010
ACM
15 years 4 months ago
A machine-checked soundness proof for an efficient verification condition generator
Verification conditions (VCs) are logical formulae whose validity implies the correctness of a program with respect to a specification. The technique of checking software properti...
Frédéric Vogels, Bart Jacobs 0002, F...
ICSE
2008
IEEE-ACM
16 years 7 months ago
Formal verification of an automotive scenario in service-oriented computing
We report on the successful application of academic experience with formal modelling and verification techniques to an automotive scenario from the service-oriented computing doma...
Maurice H. ter Beek, Stefania Gnesi, Nora Koch, Fr...
ISBI
2008
IEEE
16 years 7 months ago
Projection plane processing for sketch-based volume segmentation
Selecting a region of interest (ROI) within unsegmented volume data is one of the fundamental operations in volume data processing and analysis, yet it is difficult to perform the...
Shigeru Owada, Frank Nielsen, Takeo Igarashi, Ryo ...