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ICCS
2007
Springer
15 years 11 months ago
Formal Verification of Analog and Mixed Signal Designs in Mathematica
In this paper, we show how symbolic algebra in Mathematica can be used to formally verify analog and mixed signal designs. The verification methodology is based on combining induct...
Mohamed H. Zaki, Ghiath Al Sammane, Sofiène...
DATE
2004
IEEE
147views Hardware» more  DATE 2004»
15 years 10 months ago
Formal Refinement and Model Checking of an Echo Cancellation Unit
This article presents an approach, which combines theorem proving-based refinement with model checking for state based real-time systems. Our verification flow starts from UML sta...
Alexander Krupp, Wolfgang Müller 0003, Ian Ol...
DAC
1997
ACM
15 years 10 months ago
Formal Verification of FIRE: A Case Study
We present our experiences with the formal verification of an automotive chip used to control the safety features in a car. We used a BDD based model checker in our work. We descr...
Jae-Young Jang, Shaz Qadeer, Matt Kaufmann, Carl P...
STOC
1994
ACM
95views Algorithms» more  STOC 1994»
15 years 10 months ago
Improved non-approximability results
We indicate strong non-approximability factors for central problems: N1/4 for Max Clique; N1/10 for Chromatic Number; and 66/65 for Max 3SAT. Underlying the Max Clique result is a...
Mihir Bellare, Madhu Sudan
PLDI
2010
ACM
15 years 10 months ago
Parameterized Verification of Transactional Memories
We describe an automatic verification method to check whether transactional memories ensure strict serializability--a key property assumed of the transactional interface. Our main...
Michael Emmi, Rupak Majumdar, Roman Manevich