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FDL
2007
IEEE
16 years 1 months ago
Automatic High Level Assertion Generation and Synthesis for Embedded System Design
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
Lun Li, Frank P. Coyle, Mitchell A. Thornton
ICMCS
2007
IEEE
153views Multimedia» more  ICMCS 2007»
16 years 1 months ago
Towards Adversary Aware Surveillance Systems
We consider surveillance problems to be a set of system- adversary interaction problems in which an adversary can be modeled as a rational (selfish) agent trying to maximize his ...
Vivek K. Singh, Mohan S. Kankanhalli
156
Voted
IAT
2006
IEEE
16 years 25 days ago
Empirical Analysis for Agent System Comprehension and Verification
Comprehending and verifying agent system behavior is an arduous task when dealing with complex multiagent systems whose behaviors are sophisticated. This paper presents an approac...
Tibor Bosse, Dung N. Lam, K. Suzanne Barber
ISSS
2000
IEEE
109views Hardware» more  ISSS 2000»
15 years 11 months ago
Verification of Embedded Systems using a Petri Net based Representation
The ever increasing complexity of embedded systems consisting of hardware and software components poses a challenge in verifying their correctness, New verification methods that o...
Luis Alejandro Cortés, Petru Eles, Zebo Pen...
EUROPLOP
2006
15 years 8 months ago
A Pattern Language for Overlay Networks in Peer-to-Peer Systems
Peer-to-peer systems typically operate in large-scale, highly unreliable and insecure environments. Tackling this complexity requires good software design. Yet, many peer-to-peer ...
Dominik Grolimund, Peter Muller