—This paper describes a novel framework, called Distributed Partial Information Management (or DPIM). It addresses several major challenges in achieving efficient shared path pr...
Many emerging processor microarchitectures seek to manage technological constraints (e.g., wire delay, power, and circuit complexity) by resorting to nonuniform designs that provi...
We propose a scheme for transient-fault recovery called Simultaneously and Redundantly Threaded processors with Recovery (SRTR) that enhances a previously proposed scheme for tran...
This system paper reports on some of the advantages tangible interaction can bring to chemistry education. The paper describes the realisation of an in-house designed Tangible Use...
Data prefetching effectively reduces the negative effects of long load latencies on the performance of modern processors. Hardware prefetchers employ hardware structures to predic...
Jamison D. Collins, Suleyman Sair, Brad Calder, De...