Sciweavers

32032 search results - page 6135 / 6407
» Verified programming in Guru
Sort
View
ISPASS
2003
IEEE
15 years 12 months ago
Performance study of a cluster runtime system for dynamic interactive stream-oriented applications
Emerging application domains such as interactive vision, animation, and multimedia collaboration display dynamic scalable parallelism, and high computational requirements, making ...
Arnab Paul, Nissim Harel, Sameer Adhikari, Bikash ...
MICRO
2003
IEEE
258views Hardware» more  MICRO 2003»
15 years 12 months ago
LLVA: A Low-level Virtual Instruction Set Architecture
A virtual instruction set architecture (V-ISA) implemented via a processor-specific software translation layer can provide great flexibility to processor designers. Recent examp...
Vikram S. Adve, Chris Lattner, Michael Brukman, An...
176
Voted
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
15 years 12 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
MICRO
2003
IEEE
125views Hardware» more  MICRO 2003»
15 years 12 months ago
WaveScalar
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...
Steven Swanson, Ken Michelson, Andrew Schwerin, Ma...
PVG
2003
IEEE
138views Visualization» more  PVG 2003»
15 years 12 months ago
Sort-First, Distributed Memory Parallel Visualization and Rendering
While commodity computing and graphics hardware has increased in capacity and dropped in cost, it is still quite difficult to make effective use of such systems for general-purpos...
E. Wes Bethel, Greg Humphreys, Brian E. Paul, J. D...
« Prev « First page 6135 / 6407 Last » Next »