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CGO
2005
IEEE
16 years 12 days ago
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache
Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-p...
Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh ...
CGO
2005
IEEE
16 years 12 days ago
Maintaining Consistency and Bounding Capacity of Software Code Caches
Software code caches are becoming ubiquitous, in dynamic optimizers, runtime tool platforms, dynamic translators, fast simulators and emulators, and dynamic compilers. Caching fre...
Derek Bruening, Saman P. Amarasinghe
CGO
2005
IEEE
16 years 12 days ago
A General Compiler Framework for Speculative Optimizations Using Data Speculative Code Motion
Data speculative optimization refers to code transformations that allow load and store instructions to be moved across potentially dependent memory operations. Existing research w...
Xiaoru Dai, Antonia Zhai, Wei-Chung Hsu, Pen-Chung...
CLUSTER
2005
IEEE
16 years 12 days ago
Supporting iWARP Compatibility and Features for Regular Network Adapters
With several recent initiatives in the protocol offloading technology present on network adapters, the user market is now distributed amongst various technology levels including r...
Pavan Balaji, Hyun-Wook Jin, Karthikeyan Vaidyanat...
CODES
2005
IEEE
16 years 12 days ago
Future wireless convergence platforms
As wireless platforms converge to multimedia systems, architectures must converge to support voice, data, and video applications. From a processor architecture perspective, suppor...
C. John Glossner, Mayan Moudgill, Daniel Iancu, Ga...
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