The use of formal models for user interface design can provide a number of benefits. It can help to ensure consistency across designs for multiple platforms, prove properties such...
This paper presents VyrdMC, a runtime verification tool we are building for concurrent software components. The correctness criterion checked by VyrdMC is refinement: Each executi...
Our ability to numerically model natural systems has progressed enormously over the last 10e20 years. During the last decade computational power has increased to the stage where w...
State machine based formalisms such as labelled transition systems (LTS) are generally assumed to be complete descriptions m behaviour at some level of abstraction: if a labelled ...
Designers of SoCs with non-digital components, such as analog or MEMS devices, can currently use high-level system design languages, such as SystemC, to model only the digital par...
Ankush Varma, Muhammad Yaqub Afridi, Akin Akturk, ...