5525 search results - page 420 / 1105 » Verification of Model Transformations |
203
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DSD
2009
IEEE
15 years 4 months ago
2009
IEEE
Several traditional VHDL fault injection mechanisms like mutants or saboteurs have been adapted to SystemC model descriptions. The main drawback of these approaches is the necessi...
219
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EJWCN
2010
15 years 1 months ago
2010
Simulation studies have been the predominant method of evaluating ad hoc routing algorithms. Despite their wide use and merits, simulations are generally time consuming. Furthermo...
165
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DAC
2007
ACM
16 years 8 months ago
2007
ACM
Static worst-case execution time (WCET) analysis is done by modeling the hardware behavior. In this paper we describe a WCET analysis technique to analyze systems with function ca...
199
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DAC
2005
ACM
16 years 8 months ago
2005
ACM
Small, embedded integrated circuits (ICs) such as smart cards are vulnerable to so-called side-channel attacks (SCAs). The attacker can gain information by monitoring the power co...
156
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VLSID
2002
IEEE
16 years 7 months ago
2002
IEEE
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline v...