5525 search results - page 357 / 1105 » Verification of Model Transformations |
165
click to vote
VAMOS
2010
Springer
15 years 8 months ago
2010
Springer
We discuss the application of deontic logics to the modelling of variabilities in product family descriptions. Deontic logics make it possible to express concepts like permission a...
174
click to vote
AAAI
2004
15 years 8 months ago
2004
Model checking is a promising approach to automatic verification, which has concentrated on specification expressed in temporal logic. Comparatively little attention has been give...
171
click to vote
INFSOF
2006
15 years 6 months ago
2006
Discrete EVent Systems Specification (DEVS) formalism supports specification of discrete event models in a hierarchical modular manner. This paper proposes a DEVS modeling languag...
171
click to vote
DEDS
2002
15 years 6 months ago
2002
This article presents an extension to the timed binary Cell-DEVS paradigm. The goal is to allow the modelling of n-dimensional generic cell spaces, including transport or inertial...
164
click to vote
FDL
2005
IEEE
16 years 14 days ago
2005
IEEE
In order to address the complexities of SoC design, rigorous development methods and automated tools are required. This paper presents an approach to formal verification using mod...