Sciweavers

809 search results - page 109 / 162
» Variations in Cache Behavior
Sort
View
CGO
2004
IEEE
15 years 9 months ago
Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan d...
MMM
2009
Springer
126views Multimedia» more  MMM 2009»
16 years 2 months ago
A User Experience Model for Home Video Summarization
In this paper, we propose a novel system for automatically summarizing home videos based on a user experience model. The user experience model takes account of user’s spontaneous...
Wei-Ting Peng, Wei-Jia Huang, Wei-Ta Chu, Chien-Na...
TEI
2010
ACM
133views Hardware» more  TEI 2010»
16 years 26 days ago
Move it!: puppetry for creativity
This project studied the influence of kinesthetic intelligences on creativity in young children. To understand this relationship preschoolers were observed in their daycare setti...
Jasmine M. Williams
DATE
2006
IEEE
142views Hardware» more  DATE 2006»
16 years 2 days ago
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
ISQED
2006
IEEE
109views Hardware» more  ISQED 2006»
16 years 20 hour ago
Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher perm...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...