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DAC
1999
ACM
15 years 10 months ago
A Two-State Methodology for RTL Logic Simulation
This paper describes a two-state methodology for register transfer level (RTL) logic simulation in which the use of the Xstate is completely eliminated inside ASIC designs. Exampl...
Lionel Bening
ISSS
1998
IEEE
120views Hardware» more  ISSS 1998»
15 years 10 months ago
Application of Instruction Analysis/Synthesis Tools to x86's Functional Unit Allocation
Designing a cost effective superscalar architecture for x86 compatible microprocessors is a challenging task in terms of both technical difficulty and commercial value. One of the...
Ing-Jer Huang, Ping-Huei Xie
IWPC
1997
IEEE
15 years 10 months ago
Identifying objects in legacy systems
Many organisations are migrating towards object-oriented technology. However, owing to the business value of legacy software, new object-oriented development has to be weighed aga...
Aniello Cimitile, Andrea De Lucia, Giuseppe A. Di ...
ICCAD
1996
IEEE
140views Hardware» more  ICCAD 1996»
15 years 10 months ago
Register-transfer level estimation techniques for switching activity and power consumption
We present techniques for estimating switching activity and power consumption in register-transfer level (RTL) circuits. Previous work on this topic has ignored the presence of gl...
Anand Raghunathan, Sujit Dey, Niraj K. Jha
RTSS
1994
IEEE
15 years 10 months ago
Guaranteeing End-to-End Timing Constraints by Calibrating Intermediate Processes
This paper presents a comprehensive design methodology for guaranteeing end-to-end requirements of real-time systems. Applications are structured as a set of process components co...
Richard Gerber, Seongsoo Hong, Manas Saksena