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ASYNC
2002
IEEE
112views Hardware» more  ASYNC 2002»
15 years 11 months ago
A Negative-Overhead, Self-Timed Pipeline
This paper presents a novel variation of wave pipelining that we call “surfing.” In previous wave pipelined designs, timing uncertainty grows monotonically as events propagat...
Mark R. Greenstreet, Brian D. Winters
BCSHCI
2009
15 years 7 months ago
Photo displays and intergenerational relationships in the family home
In this paper we describe a design-orientated field study in which we deploy a novel digital display device to explore the potential integration of teenage and family photo displa...
Abigail Durrant, Alex S. Taylor, David M. Frohlich...
TVLSI
2008
140views more  TVLSI 2008»
15 years 6 months ago
A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions
We present a Mutation-based Validation Paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, ...
Jorge Campos, Hussain Al-Asaad
ET
2002
90views more  ET 2002»
15 years 6 months ago
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrappe...
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan M...
ASPDAC
2010
ACM
152views Hardware» more  ASPDAC 2010»
15 years 4 months ago
Slack redistribution for graceful degradation under voltage overscaling
Modern digital IC designs have a critical operating point, or "wall of slack", that limits voltage scaling. Even with an errortolerance mechanism, scaling voltage below a...
Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, Jo...