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94

GLVLSI
1998
IEEE

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The Chinese Abacus Method: Can We Use It for Digital Arithmetic?

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The Chinese Abacus Method: Can We Use It for Digital Arithmetic?

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Franco Maloberti, Chen Gang

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101

GLVLSI
1998
IEEE

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MDG-based Verification by Retiming and Combinational Transformations

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MDG-based Verification by Retiming and Combinational Transformations

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Otmane Aït Mohamed, Eduard Cerny, Xiaoyu Song

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140

GLVLSI
1998
IEEE

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Design of Clock Distribution Networks in Presence of Process Variations

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Design of Clock Distribution Networks in Presence of Process Variations

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Mohamed Nekili, Yvon Savaria, Guy Bois

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128

GLVLSI
1998
IEEE

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Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling

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Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling

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Irith Pomeranz, Sudhakar M. Reddy

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108

GLVLSI
1998
IEEE

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A Design-for-Testability Technique for Detecting Delay Faults in Logic Circuits

15 years 10 months ago

A Design-for-Testability Technique for Detecting Delay Faults in Logic Circuits

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Kaamran Raahemifar, Majid Ahmadi

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