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GLVLSI
2009
IEEE
167views VLSI» more  GLVLSI 2009»
16 years 1 months ago
Dual-threshold pass-transistor logic design
This paper introduces pass-transistor logic design with dualthreshold voltages. A set of single-rail, fully restored, passtransistor gates are presented. Logic transistors are imp...
Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. ...
GLVLSI
2009
IEEE
132views VLSI» more  GLVLSI 2009»
16 years 1 months ago
Multicast routing with dynamic packet fragmentation
Networks-on-Chip (NoCs) become a critical design factor as chip multiprocessors (CMPs) and systems on a chip (SoCs) scale up with technology. With fundamental benefits of high ban...
Young Hoon Kang, Jeff Sondeen, Jeffrey T. Draper
SBCCI
2009
ACM
188views VLSI» more  SBCCI 2009»
16 years 1 months ago
Low-power inter-core communication through cache partitioning in embedded multiprocessors
We present an application-driven customization methodology for energy-efficient inter-core communication in embedded multiprocessors. The methodology leverages configurable cach...
Chenjie Yu, Xiangrong Zhou, Peter Petrov
SBCCI
2009
ACM
145views VLSI» more  SBCCI 2009»
16 years 1 months ago
Pipelined successive approximation conversion (PSAC) with error correction for a CMOS ophthalmic sensor
The purpose of this work is the proposal of a 10-Bit / 1 MSPS Analog to Digital Converter (ADC) with error correction to match the requirements of a CMOS wavefront sensor for opht...
Frank Sill, Davies W. de Lima Monteiro
GLVLSI
2008
IEEE
120views VLSI» more  GLVLSI 2008»
16 years 1 months ago
SAT-based equivalence checking of threshold logic designs for nanotechnologies
Novel nano-scale devices have shown promising potential to overcome physical barriers faced by complementary metaloxide semiconductor (CMOS) technology in future circuit design. H...
Yexin Zheng, Michael S. Hsiao, Chao Huang