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ISLPED
1997
ACM
94views Hardware» more  ISLPED 1997»
15 years 10 months ago
A gate resizing technique for high reduction in power consumption
With the advent of portable and high density microelectronic devices, the power dissipation of VLSI circuits is becoming a critical concern. In this paper, we propose a post
Patrick Girard, Christian Landrault, Serge Pravoss...
ALGORITHMICA
2004
111views more  ALGORITHMICA 2004»
15 years 6 months ago
The Hausdorff Voronoi Diagram of Point Clusters in the Plane
We study the Hausdorff Voronoi diagram of point clusters in the plane, a generalization of Voronoi diagrams based on the Hausdorff distance function. We derive a tight combinatori...
Evanthia Papadopoulou
ICCAD
2007
IEEE
115views Hardware» more  ICCAD 2007»
16 years 3 months ago
Timing optimization by restructuring long combinatorial paths
—We present an implementation of an algorithm for constructing provably fast circuits for a class of Boolean functions with input signals that have individual starting times. We ...
Jürgen Werber, Dieter Rautenbach, Christian S...
ICCAD
2004
IEEE
115views Hardware» more  ICCAD 2004»
16 years 3 months ago
Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation
Abstract— This paper presents a post-route, timingconstrained gate-sizing algorithm for crosstalk reduction. Gate-sizing has emerged as a practical and feasible method to reduce ...
Debjit Sinha, Hai Zhou
GLVLSI
2006
IEEE
112views VLSI» more  GLVLSI 2006»
16 years 17 days ago
A design methodology for temperature variation insensitive low power circuits
Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable circuit operation under temperature fluctuations. A design methodology base...
Ranjith Kumar, Volkan Kursun