Sciweavers

352 search results - page 53 / 71
» VHDL
Sort
View
CAI
2004
Springer
15 years 5 months ago
An Evolvable Combinational Unit for FPGAs
A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evo...
Lukás Sekanina, Stepan Friedl
DSD
2009
IEEE
141views Hardware» more  DSD 2009»
15 years 3 months ago
A Reconfigurable Frame Interpolation Hardware Architecture for High Definition Video
-- Since Frame Rate Up-Conversion (FRC) is started to be used in recent consumer electronics products like High Definition TV, real-time and low cost implementation of FRC algorith...
Ozgur Tasdizen, Ilker Hamzaoglu
DATE
2006
IEEE
101views Hardware» more  DATE 2006»
16 years 8 hour ago
Design with race-free hardware semantics
Most hardware description languages do not enforce determinacy, meaning that they may yield races. Race conditions pose a problem for the implementation, verification, and validat...
Patrick Schaumont, Sandeep K. Shukla, Ingrid Verba...
GLVLSI
2002
IEEE
108views VLSI» more  GLVLSI 2002»
15 years 11 months ago
Protected IP-core test generation
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
Alessandro Fin, Franco Fummi
EURODAC
1994
IEEE
211views VHDL» more  EURODAC 1994»
15 years 10 months ago
Advanced simulation and modeling techniques for hardware quality verification of digital systems
synchronisation also play a fundamental role in overall system robustness. ElectroMagnetic Compatibility (EMC) and ElectroMagnetic Interference (EMI) issues also have to be conside...
S. Forno, Stephen Rochel