Sciweavers

3911 search results - page 392 / 783
» Using Operational Architecture to Model Embedded Software
Sort
View
ASPDAC
2006
ACM
133views Hardware» more  ASPDAC 2006»
16 years 25 days ago
An SPU reference model for simulation, random test generation and verification
– An instruction set level reference model was developed for the development of synergistic processing unit (SPU) , which is one of the key components of the cell processor [1][2...
Yukio Watanabe, Balazs Sallay, Brad W. Michael, Da...
CAMP
2005
IEEE
16 years 14 days ago
Principles of a CMOS Sensor Dedicated to Face Tracking and Recognition
— This paper describes the main principles of a vision sensor dedicated to the detecting and tracking faces in video sequences. For this purpose, a current mode CMOS active senso...
Dominique Ginhac, Eri Prasetyo, Michel Paindavoine...
ISCAS
2002
IEEE
124views Hardware» more  ISCAS 2002»
15 years 11 months ago
Performance optimization of multiple memory architectures for DSP
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
IFIP
2010
Springer
15 years 1 months ago
Model Checking of Concurrent Algorithms: From Java to C
Concurrent software is difficult to verify. Because the thread schedule is not controlled by the application, testing may miss defects that occur under specific thread schedules. T...
Cyrille Artho, Masami Hagiya, Watcharin Leungwatta...
IPPS
1994
IEEE
15 years 11 months ago
Building Multithreaded Architectures with Off-the-Shelf Microprocessors
Present-day parallel computers often face the problems of large software Overheadsfor process switching and interprocessor communication. These problems are addressed by the Multi...
Herbert H. J. Hum, Kevin B. Theobald, Guang R. Gao