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ASPLOS
2010
ACM
15 years 11 months ago
An asymmetric distributed shared memory model for heterogeneous parallel systems
Heterogeneous computing combines general purpose CPUs with accelerators to efficiently execute both sequential control-intensive and data-parallel phases of applications. Existin...
Isaac Gelado, Javier Cabezas, Nacho Navarro, John ...
ISCA
2002
IEEE
115views Hardware» more  ISCA 2002»
15 years 11 months ago
ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors
This paper presents ReVive, a novel general-purpose rollback recovery mechanism for shared-memory multiprocessors. ReVive carefully balances the conflicting requirements of avail...
Milos Prvulovic, Josep Torrellas, Zheng Zhang
HICSS
1995
IEEE
109views Biometrics» more  HICSS 1995»
15 years 10 months ago
The architecture of an optimistic CPU: the WarpEngine
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...
John G. Cleary, Murray Pearson, Husam Kinawi
ECMDAFA
2010
Springer
132views Hardware» more  ECMDAFA 2010»
15 years 7 months ago
An Integrated Facet-Based Library for Arbitrary Software Components
Reuse is an important means of reducing costs and effort during the development of complex software systems. A major challenge is to find suitable components in a large library wit...
Matthias Schmidt, Jan Polowinski, Jendrik Johannes...
HPCA
2007
IEEE
16 years 7 months ago
Colorama: Architectural Support for Data-Centric Synchronization
With the advent of ubiquitous multi-core architectures, a major challenge is to simplify parallel programming. One way to tame one of the main sources of programming complexity, n...
Luis Ceze, Pablo Montesinos, Christoph von Praun, ...