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HPCC
2005
Springer
16 years 4 days ago
Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture
In this paper we present an exhaustive evaluation of the memory subsystem in a chip-multiprocessor (CMP) architecture composed of 16 cores. The characterization is performed making...
Francisco J. Villa, Manuel E. Acacio, José ...
ICDCS
2007
IEEE
16 years 28 days ago
Automated Storage Reclamation Using Temporal Importance Annotations
This work focuses on scenarios that require the storage of large amounts of data. Such systems require the ability to either continuously increase the storage space or reclaim spa...
Surendar Chandra, Ashish Gehani, Xuwen Yu
PDP
2010
IEEE
15 years 11 months ago
Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
Antonio Flores, Juan L. Aragón, Manuel E. A...
ICS
1999
Tsinghua U.
15 years 11 months ago
Improving the performance of bristled CC-NUMA systems using virtual channels and adaptivity
Current high-end parallel systems achieve low-latency, highbandwidth network communication through the use of aggressive design techniques and expensive mechanical and electrical ...
José F. Martínez, Josep Torrellas, J...
IPSN
2007
Springer
16 years 23 days ago
Robust system multiangulation using subspace methods
Sensor location information is a prerequisite to the utility of most sensor networks. In this paper we present a robust and low-complexity algorithm to self-localize and orient se...
Joshua N. Ash, Lee C. Potter