4445 search results - page 228 / 889 » Use of statistical timing analysis on real designs |
151
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JPDC
2011
15 years 1 months ago
2011
Networks-on-chip (NoCs) are used in a growing number of SoCs and multi-core processors. Because messages compete for the NoC’s shared resources, quality of service and resource ...
164
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ISCAS
2006
IEEE
16 years 19 days ago
2006
IEEE
Abstract— A fast timing analysis of plane circuits via two-layer CNNbased modeling, which is necessary for the solution of power/signal integrity problems in printed circuit boar...
217
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CN
2011
15 years 1 months ago
2011
In many scenarios network design is not enforced by a central authority, but arises from the interactions of several self-interested agents. This is the case of the Internet, wher...
178
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MEMOCODE
2003
IEEE
15 years 12 months ago
2003
IEEE
In this paper, we present a technique for determining tight bounds on the execution time of assembler programs. Thus, our method is independent of the design flow, but takes into...
150
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ISCAS
2008
IEEE
16 years 1 months ago
2008
IEEE
— This paper presents models for estimating the transition activity of signals at the output of adders in Field Programmable Gate Arrays (FPGAs), given only word-level measures o...