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» Use of statistical timing analysis on real designs
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WCET
2008
15 years 8 months ago
Computing time as a program variable: a way around infeasible paths
Conditional branches connect the values of program variables with the execution paths and thus with the execution times, including the worstcase execution time (WCET). Flow analys...
Niklas Holsti
IPPS
2005
IEEE
16 years 6 days ago
Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when usi...
Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna
ECBS
2007
IEEE
145views Hardware» more  ECBS 2007»
15 years 10 months ago
Automatic Verification and Performance Analysis of Time-Constrained SysML Activity Diagrams
We present in this paper a new approach for the automatic verification and performance analysis of SysML activity diagrams. Since timeliness is important in the design and analysi...
Yosr Jarraya, Andrei Soeanu, Mourad Debbabi, Fawzi...
IEEEPACT
2003
IEEE
15 years 12 months ago
Picking Statistically Valid and Early Simulation Points
Modern architecture research relies heavily on detailed pipeline simulation. Simulating the full execution of an industry standard benchmark can take weeks to months to complete. ...
Erez Perelman, Greg Hamerly, Brad Calder
ICASSP
2009
IEEE
15 years 10 months ago
From rule-based to statistical grammars: Continuous improvement of large-scale spoken dialog systems
Statistical Spoken LanguageUnderstandinggrammars (SSLUs) are often used only at the top recognition contexts of modern large-scale spoken dialog systems. We propose to use SSLUs a...
David Suendermann, Keelan Evanini, Jackson Liscomb...