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» Use of statistical timing analysis on real designs
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ASPDAC
2005
ACM
153views Hardware» more  ASPDAC 2005»
15 years 8 months ago
Design of clocked circuits using UML
– Clocking is an essential component of any embedded system design. However, traditional design techniques are either short of clocking support or too complex for users. The Unif...
Zhenxin Sun, Weng-Fai Wong, Yongxin Zhu, Santhosh ...
BMCBI
2010
150views more  BMCBI 2010»
15 years 4 months ago
Kernel based methods for accelerated failure time model with ultra-high dimensional data
Background: Most genomic data have ultra-high dimensions with more than 10,000 genes (probes). Regularization methods with L1 and Lp penalty have been extensively studied in survi...
Zhenqiu Liu, Dechang Chen, Ming Tan, Feng Jiang, R...
ITC
1996
IEEE
96views Hardware» more  ITC 1996»
15 years 10 months ago
Analysis and Detection of Timing Failures in an Experimental Test Chip
A 25k gate Test Chip was designed and manufactured to evaluate different test methods for scan-designed circuits. The design of the chip, the experiment, and preliminary experimen...
Piero Franco, Siyad C. Ma, Jonathan Chang, Yi-Chin...
DISOPT
2007
155views more  DISOPT 2007»
15 years 6 months ago
Linear-programming design and analysis of fast algorithms for Max 2-CSP
The class Max (r, 2)-CSP (or simply Max 2-CSP) consists of constraint satisfaction problems with at most two r-valued variables per clause. For instances with n variables and m bin...
Alexander D. Scott, Gregory B. Sorkin
MICCAI
2007
Springer
16 years 7 months ago
Statistical Atlases of Bone Anatomy: Construction, Iterative Improvement and Validation
We present an iterative bootstrapping framework to create and analyze statistical atlases of bony anatomy such as the human pelvis from a large collection of CT data sets. We creat...
Gouthami Chintalapani, Lotta Maria Ellingsen, Ofri...