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» Use of statistical timing analysis on real designs
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FORMATS
2007
Springer
15 years 10 months ago
Combining Formal Verification with Observed System Execution Behavior to Tune System Parameters
Resource limited DRE (Distributed Real-time Embedded) systems can benefit greatly from dynamic adaptation of system parameters. We propose a novel approach that employs iterative t...
Minyoung Kim, Mark-Oliver Stehr, Carolyn L. Talcot...
VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
16 years 7 months ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...
EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
15 years 10 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
ICC
2007
IEEE
122views Communications» more  ICC 2007»
16 years 27 days ago
Detecting HTTP Tunnels with Statistical Mechanisms
Abstract— Application Level Gateways and firewalls are commonly used to enforce security policies at network boundaries, especially in large-sized business networks. However, se...
Manuel Crotti, Maurizio Dusi, Francesco Gringoli, ...
AIED
2005
Springer
16 years 4 days ago
The Use of Qualitative Reasoning Models of Interactions between Populations to Support Causal Reasoning of Deaf Students
Making inferences is crucial for understanding the world. The school may develop such skills but there are few formal opportunities for that. This paper describes an experiment de...
Paulo Salles, Heloisa Lima-Salles, Bert Bredeweg