As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
Performance evaluation is a central issue in the design of complex real-time systems. In this work, we propose an extension of socalled "Max-Plus" algebraic techniques to...
Remote data access from disparate sources across a widearea network such as the Internet is problematic due to the unpredictable nature of the communications medium and the lack o...
Several optimizations to the Time Warp synchronization protocol for parallel discrete event simulation have been proposed and studied. Many of these optimizations have included so...
Radharamanan Radhakrishnan, Lantz Moore, Philip A....
We consider the problem of finding association rules that make nearly optimal binary segmentations of huge categorical databases. The optimality of segmentation is defined by an o...