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VLSID
2007
IEEE
130views VLSI» more  VLSID 2007»
16 years 6 months ago
Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform
The Discrete Wavelet Transform (DWT) forms the core of the JPEG2000 image compression algorithm. Since the JPEG2000 compression application is heavily data-intensive, the overall ...
Rahul Jain, Preeti Ranjan Panda
DATE
2005
IEEE
118views Hardware» more  DATE 2005»
15 years 11 months ago
Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach
In this paper, we present a methodology for customized communication architecture synthesis that matches the communication requirements of the target application. This is an impor...
Ümit Y. Ogras, Radu Marculescu
ICCS
2003
Springer
15 years 11 months ago
Design and Evaluation of Distributed Smart Disk Architecture for I/O-Intensive Workloads
Smart disks, a type of processor-embedded active I/O devices, with their on-disk memory and network interface controller, can be viewed as processing elements with attached storage...
Steve C. Chiu, Wei-keng Liao, Alok N. Choudhary
CSMR
2004
IEEE
15 years 10 months ago
Architecture-Aware Adaptive Clustering of OO Systems
The recovery of software architecture is a first important step towards re-engineering a software system. Architecture recovery usually involves clustering. The problem with curre...
Markus Bauer, Mircea Trifu
MPC
1995
Springer
150views Mathematics» more  MPC 1995»
15 years 9 months ago
Architecture Independent Massive Parallelization of Divide-and-Conquer Algorithms
Abstract. We present a strategy to develop, in a functional setting, correct, e cient and portable Divide-and-Conquer (DC) programs for massively parallel architectures. Starting f...
Klaus Achatz, Wolfram Schulte