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ICPP
2003
IEEE
15 years 11 months ago
Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores
In chip-multiprocessors (CMPs), the number of cores and the issue width of each core presents an important design trade-off to balance the amount of TLP and ILP between multi-thre...
Magnus Ekman, Per Stenström
IPPS
2003
IEEE
15 years 11 months ago
Using Incorrect Speculation to Prefetch Data in a Concurrent Multithreaded Processor
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
Ying Chen, Resit Sendag, David J. Lilja
RSP
2003
IEEE
147views Control Systems» more  RSP 2003»
15 years 11 months ago
Cache Configuration Exploration on Prototyping Platforms
We describe cache architecture, intended for prototype-oriented IC platforms, that automatically finds the best cache configuration for a particular application. The cache itself ...
Chuanjun Zhang, Frank Vahid
FOCS
2002
IEEE
15 years 11 months ago
Implicit B-Trees: New Results for the Dictionary Problem
We reopen the issue of finding an implicit data structure for the dictionary problem. In particular, we examine the problem of maintaining Ò data values in the first Ò locatio...
Gianni Franceschini, Roberto Grossi, J. Ian Munro,...
IEEEPACT
2002
IEEE
15 years 11 months ago
An Evaluation of Data-Parallel Compiler Support for Line-Sweep Applications
Data parallel compilers have long aimed to equal the performance of carefully hand-optimized parallel codes. For tightly-coupled applications based on line sweeps, this goal has b...
Daniel G. Chavarría-Miranda, John M. Mellor...