1217 search results - page 56 / 244 » Uncertainty-aware circuit optimization |
146
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ICCAD
2008
IEEE
16 years 13 days ago
2008
IEEE
— To save power consumption, it has been shown that the clock signal can be gated without changing the functionality under certain clock-gating conditions. We observe that the cl...
152
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ASPDAC
2009
ACM
15 years 10 months ago
2009
ACM
— In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise pro...
141
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IWSOC
2005
IEEE
15 years 11 months ago
2005
IEEE
This paper explores the design and optimization of Quasi-Floating Gate MOS techniques to lowvoltage/low-power digital circuitry. The simulated power consumption of standard CMOS g...