1217 search results - page 18 / 244 » Uncertainty-aware circuit optimization |
182
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ISLPED
1995
ACM
15 years 9 months ago
1995
ACM
We consider the problem of transistor sizing in a static CMOS layout to minimizethe power consumption of the circuit subject to a given delay constraint. Based on our characteriza...
156
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ITC
1998
IEEE
15 years 10 months ago
1998
IEEE
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...
121
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ICCAD
1996
IEEE
15 years 10 months ago
1996
IEEE
We describe an algorithm for the synthesis and optimization of interface circuits for embedded system components such as microprocessors, memory ASIC, and network subsystems with ...
144
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STOC
1996
ACM
15 years 10 months ago
1996
ACM
We study the complexity of computing Boolean functions using AND, OR and NOT gates. We show that a circuit of depth d with S gates can be made to output a constant by setting O(S1...
160
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CEC
2003
IEEE
15 years 9 months ago
2003
IEEE
Evolutionary computation presents a new paradigm shift in hardware design and synthesis. According to this paradigm, hardware design is pursued by deriving inspiration from biologi...